In digital circuits, clock signals may be propagated across an integrated circuit and/or forwarded to one or more other integrated circuits. The clock signal is generally used to synchronize various operations within an integrated circuit or among multiple integrated circuits. Generally, the clock signal should have a fifty percent duty cycle. However, during signal propagation, the duty cycle can change due to propagation delays, capacitive loading, etc.
Even at lower clock frequencies, deviation from a fifty percent duty cycle may reduce timing margins of a circuit but often may be ignored without impacting proper integrated circuit operation. However, as timing margins are reduced to increase clock frequency and circuit performance, deviation from a fifty percent duty cycle may be hazardous. At very high frequencies, deviations in duty cycle may cause timing constraint violations and errors that result in improper circuit operation. Further, the duty cycle of a forwarded clock can deviate from its nominal fifty percent duty cycle due to jitter or systematic skew. Jitter may be caused by components with data-dependent power supply droop or from noise introduced into the signal. Skew may be caused by device mismatch, among other things. Therefore, what is needed is a circuit that produces a signal with a duty cycle whose deviation from fifty percent is bounded.